DS3106LN+【PDF 20/92 页】IC TIMING LINE CARD 64-LQFP

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DS3106

7.8.2.3 OC3 and OC6 Configuration

The following is a step-by-step procedure for configuring the frequencies of output clocks OC3 and OC6:

Use Table 7-8 to select a set of output frequencies for each APLL, T0 and T4. Each APLL can only

generate one set of output frequencies. (In SONET/SDH equipment, the T0 APLL is typically

configured for a frequency of 311.04MHz to get N x 19.44MHz output clocks to for use on line cards.)

Determine from Table 7-8 the T0 and T4 APLL frequencies required for the frequency sets chosen in step

Configure the T0FREQ field in register T0CR1 as shown in Table 7-9 for the T0 APLL frequency

determined in step 3. Configure fields T4CR1:T4FREQ, T0CR1:T4APT0, and T0CR1:T0FT4 as shown

in Table 7-11 for the T4 APLL frequency determined in step 3.

Using Table 7-8 and Table 7-12, configure the frequencies of output clocks OC3 and OC6 in the OFREQn

fields of registers OCR2 and OCR4 and the AOFn bits in the OCR5 register.

Table 7-13 lists all standard frequencies for the output clocks and specifies how to configure the T0 APLL and/or

the T4 APLL to obtain each frequency. Table 7-13 also indicates the expected jitter amplitude for each frequency.

Table 7-6. Digital1 Frequencies

DIG1F[1:0]

SETTING IN

MCR7

DIG1SS

SETTING IN

MCR6

FREQUENCY

(MHz)

JITTER

(pk-pk, ns,

typ)

2.048

< 1

4.096

< 1

8.192

< 1

16.384

< 1

1.544

< 1

3.088

< 1

6.176

< 1

12.352

< 1

Table 7-7. Digital2 Frequencies

DIG2AF

SETTING

IN MCR6

DIG2F[1:0]

SETTING

IN MCR7

DIG2SS

SETTING

IN MCR6

FREQUENCY

(MHz)

JITTER

(pk-pk,

ns, typ)

6.312

< 1

10.000

19.440

< 1

38.880

< 1

2.048

< 1

4.096

< 1

8.192

< 1

16.384

< 1

1.544

< 1

3.088

< 1

6.176

< 1

12.352

< 1

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